The present invention relates to integrated circuit products. More particularly, the invention is directed to an arrangement of input/output cells for application specific integrated circuits (ASICs).
In large scale integrated (LSI) circuits and very large scale integrated (VLSI) circuits, such as gate arrays and application specific integrated circuits, the arrangement of the input/output cells around the periphery is a separate design task, i.e. input/output cells are arranged more or less independently from the arrangement of arrays of gates or standard cells in the interior of the integrated circuit. Since LSI and VLSI circuits typically can provide more logic functions from interior gates and/or cells, many input/output designs for LSI and VLSI circuits are known as pad limited designs. A pad limited design occurs when the number of input and output pads, and their associated input/output cells, which can be spaced around the periphery of an integrated circuit is a limiting design factor. The methodology used for a pad limited design is straight forward. First, the number of pads (with their associated input/output cells) that the periphery is required to have, is selected. Next, the perimeter of the input/output pad region is determined from the size of the integrated circuit substrate. Given these parameters, a circuit layout program automatically spaces the input/output pads and cells equally around the periphery. The automatic layout program allots the same space to each input/output pad, and any unused space is equally distributed between pads by the layout program.
At first glance, it appears that the same design methodology and the same computer aided layout program used for pad limited design would also be applicable for non-pad limited integrated circuits. However, because of the distribution of unused space to the spacing between input/output pads, the use of a pad limited design program to a non-pad limited circuit results in a waste of otherwise usable substrate area to nonactive spacing between input/output pads and their associated input/output cells.
In pad limited designs, the distribution of inactive space in the pad region is required to reduce the tendency to latch up. In previous designs, if the inactive space between input/output cells became too small, latch-up conditions could occur. The problem of latch-up is described in U.S. Pat. No. 4,660,067 issued Apr. 21, 1987 to Ebina entitled "Complementary MOS Integrated Circuit Having Means For Preventing Latch-Up Phenomenon", and U.S. Pat. No. 4,591,894 issued May 27, 1986 to Kawakami entitled "Semiconductor Device Having A Plurality Of CMOS I/O Cells Located At The Periphery Of The Chip Arranged In A Direction Perpendicular To The Sides Of The Chip". The former patented invention prevents latch-up by extra fabrication steps (which take extra material) to inhibit the formation of the parasitic devices that cause the latch-up phenomenon, and the latter patented invention arranges its I/O cells perpendicularly so that the gain of any parasitic device is lowered. The lower gain lowers the sensitivity of the parasitic device to noise triggering. Thus, the latter patent lowers the gain by physically spacing the input/output cells (and thereby waste chip space) in order to reduce the possibility of a parasitic devices that may latch-up.
It is, therefore, an object of the present invention to provide a method and arrangement of input/output cells for non-pad limited designs that do not waste space in the input/output pad region.
It is another object of the present invention to provide a method and arrangement of input/output cells that are virtually immune to latch-up.
It is a further object of the present invention to provide a method and arrangement of input/output pads and cells that may be laid out by a computer aided integrated circuit program.